Spring 2009
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AZ SOLID™ Coating for Double Patterning Applications

Aggressive process development is well underway to enable IC manufacturers to begin 32 nm half-pitch volume production using immersion double patterning (DP) by 2013. A multitude of DP techniques are being pursued, with litho-etch-litho-etch (LELE) a leading candidate for logic applications. However, LELE introduces several significant challenges including heightened process complexity as a result of using two etch steps, and dramatically higher cost of ownership (COO).

Current Technology for Double Patterning

Litho-Etch-Litho Etch

Figure 1. Process flow for litho-etch-litho-etch double patterning.

Figure 1. Process flow for litho-etch-litho-etch double patterning.

Therefore, to lower cost and simplify the DP process, suppliers of lithographic materials are investigating methods to enable litho-litho-etch (LLE) technology by incorporating an intermediate process step that modifies an existing resist structure so that it can be overcoated with a second resist without intermixing. This process is frequently referred to as "resist freezing".

AZ Electronic Materials has identified numerous requirements that must be achieved for the spin-on freezing materials to deliver production-level performance, among which are minimal CD change throughout the freeze process and no impact from external metrology requirements such as CD-SEM analysis. In addition to stable CD performance, there should be minimal first pattern top loss during the process along with no added scumming, defectivity or feature bias impacts. For optimal performance in a high volume manufacturing environment, such freeze processing should be compatible with a wide range of immersion resists for best COO and track utilization. Ideally, the double patterning technology (DPT) process should allow for the same resist to be used for first and second layers in order to minimize cost and complexity from related mask optical proximity compensation (OPC) and etch perspectives.

AZ has recently developed the SOLID™ (Spin-On Liquid to Inhibit Dissolution) process, which is a solution for double patterning that requires only a single etch step, and satisfies the performance and manufacturing requirements identified above. The SOLID™ process is applied after the first exposure, and consists of the SOLID™ coating, followed by soft bake, a deionized water or TMAH rinse, and a freezing bake.

DPT Process using AZ® SOLID

Spin-On Liquid to Inhibit Dissolution

Figure 2. The SOLID™ process eliminates the need for a second etch. This reduces DP process complexity and cost.

Figure 2. The SOLID™ process eliminates the need for a second etch. This reduces DP process complexity and cost.

Performance of the freezing process using the AZ SOLID™ method has been thoroughly demonstrated using AZ ArF-1C5D BARC and a production 193 nm resist using an NA = 0.85 scanner and a 6% attenuated phase shift mask. Critical dimensions and profile of the first pattern were verified to be stable throughout the process, and minimal resist loss was confirmed.

Freezing Process with AZ® SOLID™

Figure 3. CDs and profiles of the first pattern were stable throughout the process, and minimal resist loss was experienced.

Figure 3. CDs and profiles of the first pattern were stable throughout the process, and minimal resist loss was experienced.

To be successful in volume manufacturing, any newly developed process must be highly robust. Experimental studies evaluating X-Grid Contacts with SOLID™ film thicknesses ranging from 55 nm to 105 nm showed no dependency on the SOLID™ coating film thickness, freeze bake temperatures, or development time.

X-Grid Contact: Effects of Development Time

Figure 4. Varying SOLID™ developer time from 10 seconds to 90 seconds had minimal impact on X-Grid Contracts.

Figure 4. Varying SOLID™ developer time from 10 seconds to 90 seconds had minimal impact on X-Grid Contacts.

CD Uniformity was also studied to ensure that the SOLID™ process would satisfy aggressive double patterning requirements. As shown in the following table, CDU averages and sigma values consistent to those achieved after first litho, were maintained across both first and second images using double patterning. Defectivity performance was also verified with results after the SOLID™ process at 0.13 defects/cm2 and only 0.40 defects/cm2 following a simulated DP process; thereby confirming the SOLID™ process did not have a significant impact on defectivity.

CD Uniformity of SOLID™ Process

Figure 5. CDU averages and sigma values consistent to those achieved after first litho were maintained across both first and second images using double patterning.

Figure 5. CDU averages and sigma values consistent to those achieved after first litho were maintained across both first and second images using double patterning.

The transition to the 32 nm half-pitch will require IC manufacturers to adopt immersion double patterning, which presents challenges that include increased cost and added process complexity. Therefore, resist suppliers are developing innovative solutions to minimize the impact of DP integration for customers. For litho-litho-etch DP applications, AZ SOLID™ spin-on freezing materials allow customers to implement the DPT freeze approach with their existing resist portfolio, while delivering a production capable process having minimal resist top loss, negligible CD change, and no added defectivity impact.

AZ continues to enhance the SOLID™ materials through intense collaboration with major device manufacturers toward a production-worthy solution for 3X nm and beyond design rule devices.

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For more information please contact:
Gregg Espin
AZ Electronic Materials
gregg.espin@az-em.com
www.az-em.com

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