IC Knowledge LLC President, Scotten Jones, updated LithoVision guests on the “Evolving Semiconductor Technology Landscape, and What it Means for Lithography.” His in-depth presentation provided key insight on NAND, DRAM and logic technologies, as well as the central roles that i-line, KrF, and ArF technologies will continue to play in years to come.
For the last fifteen years or so, 2D NAND has had the tightest lithographic pitches and fastest scaling path of the technologies. Recently however, 2D scaling has become increasingly difficult to realize because of device performance issues. As a result, 3D has now replaced 2D NAND, enabling scaling by adding layers in the third (layer) dimension instead of by shrinking lithographic dimensions. The most challenging 3D feature to produce is the channel hole, due to its ever-increasing high aspect ratio etching/filling requirements, as well as a relatively small diameter of ~100 nm (Figure 1A).
Figure 1A. 3D has now replaced 2D NAND, enabling scaling by adding layers in the third dimension instead of by shrinking lithographic dimensions (left image). Figure 1B. 3D NAND 128L processes could use up to 60 masks, with roughly 80% of the layers employing i-line and KrF lithography.
Jones described how 3D NAND fabrication consists of three main phases: CMOS fabrication, memory array formation, and interconnect. In moving to a 3D approach, processing complexity increases, thereby leading to the use of more masks. When considering NAND mask counts vs. 3D layers for 128L processes, mask counts can run upwards of 60, with roughly 80% of the layers actually employing i-line and KrF lithography (Figure 1B). Bit density is defined as the number of gigabits of memory on the die divided by the die size. The transition from 2D NAND to 3D enables continued bit density scaling by using the third dimension, and bit growth density has risen from approximately 0.5 Gb/mm2 to 5.0 Gb/mm2 since 2010.
Figure 2A. DRAM nodes are defined as the smallest half-pitch for the device (left image). Figure 2B. DRAM scaling has become a complex optimization battle.
Addressing DRAM trends, Jones explained that DRAM nodes are now defined by the smallest half-pitch for the device (Figure 2A). DRAM presents a number of unique challenges as the capacitors are fabricated at the limits of mechanical stability, wherein a titanium nitride storage node is formed, and then has a dielectric layer and top plate deposited over it. Dielectrics having higher k (dielectric constant) values have lower band gaps, and therefore higher leakage. Therefore, DRAM scaling has become a complex optimization battle to achieve the lowest capacitance value, while also minimizing leakage, and optimizing the peripheral circuitry (Figure 2B). IC Knowledge LLC’s analysis of Samsung DRAM parts indicated 40+ masks are needed at the 18 nm and 15 nm nodes, with KrF replacing the lion’s share of i-line layers at the 15 nm node, and ArF immersion maintaining roughly 30% of the masking layers for both nodes (Figure 3A). Jones reported that DRAM bit growth for the individual companies appears to be flattening out, with DRAM densities across several chipmakers achieving increases from 0.05 Gb/mm2 to 0.5 Gb/mm2 in the past eight years (Figure 3B).
Figure 3A. i-line and KrF play a large role in DRAM processing, with ArFi used for approximately a third of the advanced masking layers at the nodes shown (left image). Figure 3B. Jones reported that DRAM bit growth for the individual companies appears to be flattening out.
Jones also showed logic pitch trends for contacted poly and minimum metal (Figure 4A), and highlighted a number of technologies. He gave an overview of gate all around (GAA) processing, and reported that while recent 3 nm IMEC work suggested FinFETS are a viable solution, they require the application of multiple scaling boost options, whereas nanosheets actually offer greater margin. He commented that although nanowires provide the best electrostatics, FinFETS provide superior drive current performance, and nanosheets are able to tune those tradeoffs for optimum performance.
Figure 4A. Jones showed logic pitch trends for contacted poly and minimum metal (left image). Figure 4B. There is potential for logic 2D to 3D scaling as well.
In the future, there are promising options for logic 2D to 3D scaling as well (Figure 4B). CFETS (complementary FETS) stack nFETS and pFETS to enable scaling without requiring a lithographic shrink, and CFETS incorporating many layers could even relax lithographic scaling. Jones shared IC Knowledge’s analysis of logic mask counts for a foundry with 14 nm and 10 nm processes indicating that each employed over 30 ArFi masks for the most critical layers (Figure 5A). Projections for first generation 7 nm processes used only optical lithography as well, as Jones expects EUV won’t enter use until the 2nd and 3rd generation 7c processes (EUV for contacts and 1x vias), as well as 7+ (EUV for contacts, 1x vias, and 1x metal) processes. This detailed mask layer breakdown for each of the various device types underscores the substantial role that i-line, KrF, and ArF technologies continue to play.
Figure 5A. A detailed foundry logic mask breakdown underscores the substantial role that i-line, KrF, and ArF technologies play (left image). Figure 5B. Scaling will continue, but with challenges like rising mask counts.
Jones summarized his informative presentation by reminding the audience that the NAND transition from 2D (lithography driven-processing) to 3D (etch and deposition-driven processing) relaxes pitches substantially, but warned that mask counts will rise due to string stacking (Figure 5B). He also cautioned that DRAM scaling is facing fundamental physical limits and the path forward isn’t clear beyond the next few nodes. Jones believes that logic will continue to scale lithographically, but limits to 2D scaling are on the horizon. In conclusion, he noted that CFETS may offer a 3D scaling path forward that could relax lithographic dimensions, much like what has been achieved with NAND devices.