At the annual Nikon conference, Dr. Ben Rathsack, Senior Director at Tokyo Electron America, reported that 3D architectures and continued scaling will require advances in patterning technology. He stated that edge placement error (EPE) is the fundamental scaling challenge. Rathsack described the Patterning “CFP” tradeoff triangle consisting of: Complexity and Cost in the patterning scheme, Flexibility in the design; and Performance, mostly in edge placement error (Figure 1A). Patterning challenges causing CD variation include line roughness (LER/LWR), pattern profile (leaning), etch clogging, and loading effects. In addition, he highlighted overlay factors such as alignment of cuts and blocks to grids, vias to metal lines, and alignment of holes at multiple Litho Etch steps. Numerous factors impact edge placement error (Figure 1B).
Figure 1A. Rathsack described the Patterning “CFP” tradeoff triangle (left image). Figure 1B. He emphasized that numerous factors impact EPE.
Formation of the grid is the first step requiring improvement. For instance, in self-aligned quad patterning (SAQP), recent changes in resist processing have improved robustness and verticality of the spacer mandrels (Figure 2A). Additionally, he explained that etch smoothing processes, stress engineering of the mandrel, and various reshaping of mandrel profiles have been shown to improve LER and CDU. These methods were combined in a co-optimization flow, and he showed data that demonstrated reduced grid variability (Figure 2B).
Figure 2A. SAQP using a photoresist mandrel can achieve CDU comparable to SAQP using a double hard mask mandrel approach (left image). Figure 2B. Rathsack reported that material/etch co-optimization can greatly reduce grid variability.
Another new way of improving self alignment processes is through the use of “multi-color etch selectivity,” in which the etch process is itself sensitive to the appropriate mandrel layer in a spacer/cut process. This is shown schematically in Figure 3A and Figure 3B.
Figure 3A. Multi-color etch selectivity application (left image). Figure 3B. Schematics of two possible combinations.
The topic of selective chemistries leads to selective deposition and etch, and hence to a kind of bottom-up lithography. While top-down lithography has been the mode of operation for many years (Figure 4A), Rathsack explained that one example of bottom-up lithography is self-alignment with selective deposition – metal on metal or dielectric on dielectric. The classic example is, of course, directed self-assembly (DSA) for L/S and Hole pitch multiplication (Figure 4B).
Figure 4A. Rathsack highlighted a paradigm shift to self-alignment and bottom-up approach to lithography (left image). Figure 4B. Bottom-up lithography includes self-alignment and self-assembly solutions.
An evaluation of selective metal on metal deposition demonstrated successful growth of Ruthenium (Ru) on Tungsten (W) only (Figure 5A). A Quasi-Atomic Layer Etch (ALE) concept was also shown where a cyclic process of fluorocarbon film adsorption and activation was used in precisely controlled and high selectivity etch processing. Rathsack commented that atomic control of film removal is required for improved selectivity. He showed that a Quasi-ALE process enabled a highly selective and complete etch in a self-aligned contact (SAC) structure—with substantial improvements compared to a conventional reactive ion etch (RIE) (Figure 5B).
Figure 5A. Selective deposition has been used for metal on metal applications (left image). Figure 5B. A Quasi-ALE process enables high selectivity and complete etch for SAC structures.
In summary, Rathsack reminded the audience that edge placement error is the central scaling challenge, and that there are a number of innovative ways to address its many contributors. He stressed that a patterning paradigm shift to self-alignment and bottom-up approaches will be essential in continuing to advance patterning technology.