Kohji Hashimoto, Director of the Advanced Memory Development Center for Toshiba Storage & Electronic Devices Solutions Company, delivered an engaging and highly informative presentation at the Nikon technical symposium held earlier this year. This presentation provided invaluable insight on Toshiba’s viewpoint of “Lithography in the 3D Memory Era," and included discussion of NAND Flash memory trends, as well as the process paradigm shift in 3D memory, and roles of lithography in 3D memory.
Hashimoto-san identified key NAND market trends from 2000 to 2020 including expansion of NAND applications and increasing device density, occurring in parallel with the decline in price per bit. In 2015, Toshiba announced their 48-layer BiCS 3D Flash Memory sample to boost capacity and performance. He explained that 2D NAND flash uses floating gate (FG) transistors that are connected in a horizontal direction for a NAND string. NAND 2D memory delivers higher density through patterning of smaller structures. In contrast, Toshiba BiCS Flash 3D technology incorporates the stacking of vertical NAND gate arrays to make a NAND string vertically. In this situation, higher density memory is achieved by layer stacking combined with the patterning of smaller structures (Figure 1A).
Figure 1A. NAND 2D memory delivers higher density through patterning of smaller structures. Toshiba BiCS Flash 3D technology delivers higher density memory by layer stacking combined with the patterning of smaller structures (left image). Figure 1B. Hashimoto-san discussed a vital new relationship with synergistic technology development for litho and dry etch.
For 2D memory, technology development for lithography integration, exposure tool/overlay, resist and processing, and mask control was done separately from dry etch technology development that includes conductor etch, dielectric etch and the removal process. The patterning process driver for 2D technology was lithography, while dry etching supported the patterning process. However, in 3D memory there is a paradigm shift wherein dry etching becomes the patterning driver. This necessitates a vital new relationship with synergistic technology development for litho and dry etch. Hashimoto-san identified three pivotal areas including: 1) dry etch technology as the 3D patterning driver 2) 3D-specific lithography technology, and 3) lithography technology for dry etching (Figure 1B).
Dry etch technology as the patterning process driver was discussed first. Dry etching for 3D memory incorporates three crucial processes. One process is multi-layer etching, which requires tight feature control for a small trench or a slit with a high aspect ratio. This is the most critical because different (conductor/dielectric) materials are etched repeatedly. High aspect ratio contact (HARC) etching requires varied aspect ratio etching and tight CD control. In contrast, staircase etching requires high selectivity with tighter CD control, and is heavily dependent upon help from lithography. In a high aspect ratio dry etch, a high selectivity etch process with a deposition process is used. In this process, the etch down to the mask generates deposition on the top of the mask, which can cause clogging at the top of the spaces between the lines. This clogging decreases the ion/radical flux that can reach to the bottom. To mitigate this, a deposition removal step is included during substrate etching (Figure 2A). In this type of cyclical etching process, the cycle count and timing for the etch step and deposition process must be optimized for top width/mask erosion and the substrate etched profile.
Figure 2A. The etch down to the mask generates deposition on the top of the mask, which can cause clogging at the top of spaces between the lines. To mitigate this, a deposition removal step is included during substrate etching (left image). Figure 2B. Hashimoto-san highlighted 2D vs. 3D memory-specific concerns for lithography.
Hashimoto-san next discussed 3D-specific lithography technology. He described technology challenges across many process areas and highlighted 2D vs. 3D memory-specific concerns (Figure 2B). In the case of 2D memory, exposure tool issues mainly involved low k1 imaging and immersion-related concerns, whereas 3D memory has added complexity with focusing on wafer topography. He reported that the new optical design and sensor layout used in the Nikon S62X/S63X scanner autofocus system reduces these types of process-dependent effects and enhances edge focus accuracy (Figure 3A). He commented that such technology is very powerful for focusing on 3D memory wafer topography.
Figure 3A. The new optical design and sensor layout used in the Nikon S62X/S63X scanner autofocus system reduces process-dependent effects and enhances edge focus accuracy (left image). Figure 3B. In-plane displacement data (post dep – pre dep) and overlay results comparing two deposition stages highlighted clear deposition stage dependencies.
Wafer warping and non-visible hardmask issues also contribute to 3D-specific overlay challenges. Alignment is typically performed to the hardmask layer as the substrate alignment mark isn’t visible. Hashimoto-san showed in-plane displacement data (post deposition – pre deposition) and overlay results comparing two deposition stages, which highlighted clear deposition stage dependencies (Figure 3B). He warned the audience that it is imperative to control the hardmask process for overlay in 3D memory. When considering metrology and inspection for 3D memory, there is a need for wide range and multi hole measurement capabilities under these thick material conditions. In the case of staircase processes, accurate CD measurement across a range of several microns is necessary, whereas accurate CD measurements for many holes across a one micron square measurement area is mandatory for hole processes.
Hashimoto-san summarized his presentation by reminding the audience that the transition to 3D memory involves a paradigm shift in thinking and technology development (Figure 4). The patterning process driver is changed from lithography to dry etch, and the two must have a new integrated approach. In order for dry etching to drive 3D patterning, stacked multi-layer etching, high aspect ratio contact etching, and staircase etching techniques are vital processes. He reiterated that in 3D-specific litho technology, “Those who commanded the thicker material would reign over the 3D world!!” He emphasized that dry etch will require lithography support for 3D memory, and encouraged litho and dry etch engineers to combine their skills and collaborate for ultimate success.