At the recent LithoVision technical symposium, Dr. Naga Chandrasekaran, Vice President of Process Research and Development at Micron Technology gave an exceptional keynote speech addressing the “Memory Business and Technology Perspective.” Chandrasekaran said that the worldwide semiconductor market was roughly over $300 billion in 2015, with memory contributing to ~$78 billion of the total market. He believes that DRAM and NAND memory bit growth demand will continue as new applications and needs emerge. NAND growth will be met through continued 3D NAND scaling, which might drive the need for new wafer capacity, while DRAM demand will be satisfied by technology investment (Figure 1A). It was noted that long-term memory growth will be augmented by emerging memories such as 3D XPointTM. Further diversification in end memory markets is anticipated as PC DRAM bit growth slows and transitions to increased Mobile and Server & Networking bit growth. The NAND end market mix is also changing with Mobile and SSD growth.
Figure 1A. NAND and DRAM growth increase into diversified end markets driving sustained demand (left image). Figure 1B. Scaling challenges necessitate a comprehensive process solution.
Chandrasekaran explained that bit growth can be achieved by further technology scaling, through limited scaling in conjunction with increased wafer capacity, and/or by disruptive technologies replacing conventional memory. Technology scaling can hold growth back; for instance, DRAM scaling has faced increasing challenges with array patterning. As a result, there has been a continuous reduction in bit growth improvements due to technology scaling challenges. He cautioned that significant innovation will be needed to enable continuous scaling and improve bit growth.
DRAM scaling challenges include capacitor structure scaling and materials innovation for bit line and word line scaling. In addition, overlay and patterning demands continue to drive scaling/cost limitations, necessitating a comprehensive process solution (Figure 1B). He believes that continued bit growth in NAND technology can only be enabled by the transition to and scaling of vertical NAND (V-NAND). This comes with its own challenges, including high aspect ratio (HAR) processing and some demanding planarization steps. These present wafer shape and stress management challenges, which in turn impact alignment and overlay (Figure 2A).
Figure 2A. Vertical NAND presents its own challenges (left image). Figure 2B. Areas for scaling enablement.
With that in mind, Chandrasekaran emphasized that scaling enablement is dependent upon: 1) significant innovation in the areas of equipment, materials, and controls capability; 2) improvements in manufacturability; and 3) materials advances (Figure 2B). Speaking about the key lithography enablers for memory scaling in particular, Chandrasekaran identified overlay, CDU for pitch multiplication/double patterning, materials development, metrology, CD scaling, and new patterning techniques. DRAM scaling continues to demand reduced overlay and advanced control capability, which necessitate an all-around process solution, as compared to scanner hardware advances only. He warned again that 3D NAND presents unique alignment and overlay challenges that are driven by wafer shape and stress.
Pitch multiplication and double patterning continue to enable scaling, while CDU performance is now influenced by a variety of steps and process areas. Chandrasekaran commented that compensation techniques are helping to maintain the CDU pace, but additional improvements are necessary. Resists require improved line width roughness (LWR) and profiles to enable pitch and CDU scaling (Figure 3A). In addition, downstream processing is adding problematic thermal constraints with regard to films for high temperature steps, as well as low temperature processing needs driven by new memory technologies. He noted that 3D scaling also incorporates unique etch processes that require thick resists with very tight overlay control.
Figure 3A. New scaling methods require further materials development (left image). Figure 3B. 3D scaling involves a number of specialized challenges.
Metrology is an essential component of achieving the requisite overlay and Chandrasekaran conveyed that mark engineering, the measurement tool, sampling strategy, and control methodologies are all critical. He suggested that the industry is facing an inflection point between image-based and diffraction-based overlay schemes. While it’s not clear whether one is completely better than the other, depending on process complexity they present unique advantages and might co-exist. 3D scaling presents challenges when the number of tiers increases and new hard mask films are needed (Figure 3B). These films have different optical properties, thereby degrading alignment and registration signals. Global stress management is also crucial because wafer chucking becomes more difficult, there is increased process contribution to overlay, and high volume manufacturing will require feedforward wafer shape overlay corrections to improve performance.
Looking at the cost and complexity drivers for DRAM scaling, Chandrasekaran highlighted that the increased lithography layers per module due to pitch multiplication have an impact on cost, cycle time and space. Other factors must be considered, such as critical levels needing improved alignment/overlay, CD and focus management, and advanced automation and control solutions. He said that EUV is one of the likely alternatives for continued pattern scaling as it presents simplified process flows that can enable contact and complex pattern shrink, but wondered whether cost performance can be enabled at the right time (Figure 4A). In contrast, DSA is ideal for dense L/S and contacts, but its current performance does not yet exceed that of SAQP for LER/CDU or cost. He questioned whether EBDW or NIL can match or surpass EUV targets, or if any of these alternate lithography technologies can enable cost effective scaling on time.
Figure 4A. There are questions whether any of these alternate lithography technologies can enable cost effective scaling on time (left image). Figure 4B. Litho plays a continued role in memory scaling and presents many opportunities for the industry.
Summarizing his presentation, Chandrasekaran reiterated that the long-term memory industry dynamics are favorable. DRAM and V-NAND scaling and other new memory products present a number of technical challenges and great opportunities. In order for scaling to continue, noteworthy innovations in equipment, materials, and control capabilities will be needed. Additionally, the cost of the solutions will be an essential factor in maintaining $/Gb reduction node over node. He reminded the audience that lithography continues to play a vital role in DRAM scaling, while V-NAND presents new and unique complexities (Figure 4B). In closing, he challenged the litho community to take advantage of these many opportunities.