Speaking at the annual Nikon lithography conference, Dr. Mike Adel, Senior Director of Applications at KLA-Tencor addressed the need for computational methods for CD and overlay metrology in next-generation litho. He said that computational methods will be used in CD and overlay metrology, that computational target design will in particular be used in process control, and that computational lithography will be used in optimizing overlay target design and placement.
For overlay target design, Adel cited a number of reasons for using computational methods. With the delays in EUV lithography, 193i multiple patterning is coming in to greater use, and the number of layers is increasing (Figure 1A). This has led to increasing complexity in overlay mark design as the marks are segmented or otherwise optimized for particular layers. Opacity of new film stack materials also affects mark design and measurement sensitivity, constraining metrology pitches. Thus, a computational target design flow is needed (Figure 1B).
Figure 1A. Adel cited a number of reasons for using computational methods for overlay target design (left image). Figure 1B. A computational target design flow is needed.
This flow includes stack and topography input that leads to a model, as well as lithographic and patterning design rules that provide target design of experiment (t-DOE) constraints. Adel warned that the scale of the target design of experiment can quickly rise to include hundreds or thousands of geometric permutations, multiplied by the number of metrology tool setups.
Process variation also has to be included in the flow; for instance, experiments at different wavelengths can demonstrate significantly different responses across the nominal stack and process variation conditions. Therefore, the target t-DOE domain must be used in conjunction with the process variation (Pvar) domain to identify the optimal target and recipe (Figure 2A).
Figure 2A. Target t-DOE domain must be used in conjunction with the process variation domain to identify the optimal target and recipe (left image). Figure 2B. Offsets between post-develop and post-etch metrology should be zero, but that isn’t generally the case.
In the process control part, overlay management strategy employs a tight control loop based on high sampling rates post-develop with lower sampling rates for post-etch metrology. Ideally the offset between those two metrology steps should be zero, but that isn’t generally the case (Figure 2B). This comprehensive overlay management process necessitates that the metrology target design must be successful in a single design cycle. Adel showed that incorporating feed-forward of spectroscopic ellipsometry (SE) film measurements improves simulation to measurement matching for more accurate target design models.
Finally, computational design’s use in process control can be enabled by enhancing target design rules with PROLITH. Although historical methods restrict pitches and CDs, Adel explained that virtual experiments using PROLITH modeling can provide a more comprehensive set of design rules to improve process flexibility. This frees the designer to use more creativity in mark design. A sample of such analysis is the use of Zernike sensitivity analysis (where the Zernike coefficients describe placement errors on the wafer) to look at pattern-placement errors (PPE) between different targets and the device being printed (Figure 3A).
Figure 3A. Virtual experiments using PROLITH modeling can provide a more comprehensive set of design rules (left image). Figure 3B. Computational litho helps mitigate printability risks and reduce metrology feature placement errors as well.
In closing, Adel reminded the audience that design rules below 10 nm place additional reliance on computational CD metrology. Computational overlay metrology target design is also becoming essential, and requires understanding of the target and process permutation space as well as landscape accuracy analysis. In addition, SE film metrology plays a key role in accurate target design models. Computational lithography helps mitigate printability risks and reduce metrology feature placement errors also (Figure 3B). This in turn can reduce the offsets in the overlay process control loop to support litho overlay management.