Dr. Jérôme Hazart delivered an update on directed self-assembly (DSA) at the Nikon symposium held in February. The Computational Litho Group Technical Manager provided an up-close view of CEA-Leti’s work with DSA block copolymers for via layers, and emphasized the compatibility and potential cost benefits for contact multiplication with DSA/193 nm immersion lithography.
Hazart reported that the cost per gate has steadily dropped from the 90 nm node to the 28 nm node but started to increase again at the 20 nm node (Figure 1A). The price increases are mainly attributed to the use of multiple patterning and the need for very tight process control. Hazart warned that this will be further intensified in the future by the price of EUV scanners, when they reach sufficient cost-effectiveness for implementation. It is not readily apparent how advanced nodes like 10 nm and beyond can be done affordably. Hazart’s presentation explored ways that DSA could provide a competitive and/or complementary solution for some next-generation layers.
For a 10 nm node via layer gridded design, 193i single patterning can’t be used because the characteristic pitch of 48 nm is too small. Switching to 193i double patterning will solve that problem, but, there are higher costs associated with the additional masks, as well as more costly overlay capability (Figure 1B). As an alternative, Hazart described directed self-assembly using a grapho-epitaxy process, a method that involves nano-patterning by self-assembly of block copolymers (BCP), localized with lithography patterning guides.
The DSA process is not defect free, so Hazart provided details of how innovative planarization schemes can be used to solve pattern density defects (Figure 2A). The proprietary Leti planarization flow incorporates block copolymer over-thickness filling, followed by self-assembly annealing, then etch-back and PMMA removal. This technology delivers significant imaging improvements (Figure 2B).
Regarding pitch requirements, he showed results with dense, semi-dense, and isolated images all taken on the same wafer and noted the full control of the BCP self-assembly through pitch. The naturally occurring pitch, L0, can be tuned with BCP composition, and he showed example images ranging from 22 nm to 51 nm. There is not a clear limitation on the largest L0 achievable, but Hazart noted that none can currently satisfy the 10 nm node requirement of 68 nm.
Returning to his initial example comparing single vs multiple patterning capabilities, Hazart proposed using 193i in conjunction with DSA BCP to pattern the desired “necks” for the vias. In this scheme, the 193i exposure prints a peanut-shaped guide pattern for the BCP-formed vias. This skirts the pitch requirement since the guide patterns have isolated vias within them. This is shown below (Figure 3); the question then becomes one of whether 193i litho can form such patterns.
Hazart then worked through an example of using 193i lithography to do just that. The complex patterns can be formed using inverse-lithography OPC on the mask combined with source optimization (Figure 4A).
Figure 4A. The complex patterns can be formed using inverse-lithography OPC on the mask combined with source optimization (left image). Figure 4B. A BCP model predicts the combined overlay error of the guide pattern and the BCP structures within it will yield an overall overlay value of 3.0 nm or so.
Litho modeling has confirmed that such features can be printed with a PV band of 6-9 nm. Following that, the BCP fills in the structures. A BCP model has predicted that the combined overlay error of the guide pattern and the BCP structures within it will yield an overall overlay value of 3.0 nm or so, within needs for the 10 nm node (Figure 4B). LETI has already investigated such structures albeit printed without source optimization (Figure 5A).
In summary, Hazart reported that modeling and initial exposure results obtained by CEA-Leti have been promising, and that DSA cylindrical block copolymers offer a realistic alternative to via layer multiple patterning in order to reduce cost (Figure 5B). His team believes that with appropriate BCP implementation, DSA can enable 193i-only, EUV-free fabs, down to the 10 nm node and beyond – and successfully maintain the cost per gate.