There is no shortage of technical challenges at future nodes, and experts from across the lithography supply chain discussed their views and possible solutions at the LithoVision symposium earlier this year. Dr. Kevin Lucas, Product Engineering Manager at Synopsys, kicked off the supplier discussions with a focus on integrated EDA and OPC challenges for next generation technology. Lucas commented that the wry view “The end of optical lithography is always 7 years away,” still appears true for advanced development as we approach the 10 nm and 7 nm nodes. He explained however, that shrinks are not the only scaling occurring. For instance, vertical devices will enable product scaling without reducing pitch or CD.
Optical lithography has numerous obstacles in scaling to 7 nm including increasing mask count, tighter overlay control, smaller CDs and total CD control. It was explained also that the EDA/OPC options are increasing dramatically. Lucas highlighted that at 28 nm there were only 5 new options for improving litho: LE-cut, source mask optimization (SMO), rule-based assist features (RBAF), retargeting, and etch shrinking; at 14/16 nm this increased to 8 options, 10 nm presents 21 options, and 7 nm has 71+ options (Figure 1A). Technical difficulty and especially complexity have increased. As a result, the EDA/OPC challenge is to provide better technology that is easier to customize. There are technical requirements for scaling to 7 nm (Figure 1B), such as more accurate model forms for materials and resists, better assist feature (AF) placement, and added flexibility in feature shapes to increase process windows. In addition, easier tool customization and better visualization/analysis tools are needed for the 7 nm node as well as non-pitch scaling.
|Figure 1A. Lucas highlighted that the number of new EDA/OPC options are increasing rapidly (left image). Figure 1B. He described EDA/OPC technical requirements for scaling to 7 nm.|
There are a number of Joint OPC work options with the potential to address 7 nm technical issues. Resolution and CD control may benefit from increased flexibility in the mask pattern with multi-beam e-beam writing; smaller assist features on the mask for finer diffraction and printing control could help process windows; better understanding of resist processes could aid high accuracy compact modeling of future resists; and scanner or reticle- specific systematic overlay corrections could perhaps be achieved through OPC. Lucas further explained that from the EDA view, directed self-assembly (DSA) is a variant of self-aligned double patterning (SADP) and very restrictive design rules are required (Figure 2A). It is believed the EDA focus for DSA should be on optimization of the local template shape and reducing film planarity issues.
He concluded that 10 to 7 nm and other scaling will use a great deal of optical lithography, but there are issues to resolve. Intricacies and options are growing quickly, so user complexity must be reduced. Lucas reminded the audience there are numerous ways that EDA/OPC can work with partners to advance capabilities.
Dr. Mark Smith, Research Scientist and Director of the Advanced Development group for the 5D division at KLA-Tencor, reinforced this theme of increasing complexity in his discussion of the challenges of computational lithography. He explained that computational lithography evolved from a simple optical model for scanners, and then a photoresist model was added to provide a quantitative model of through-pitch response and of process window depth of focus. This progressed onward to the complex models used today. Smith explained that self-consistent field theory can be used to predict DSA structures, and the focus and dose responses of DSA template shapes can be calculated to determine the interaction between lithography and the DSA structure. He showed an example with DSA center-to-center separation of 32 nm and reported that the DSA center-to-center process window (overlay) is smaller than the nominal CD process window for the guide structure (Figure 2B).
Metrology models have also progressed significantly, and Smith reported KLA-Tencor has built a physically-based SEM emulator to produce more realistic “pictures” of a simulated result, as well as CD measurements that mimic the physical process of the CD SEM. He explained that standard edge-detection algorithms for the SEM can be applied to images, and this can help understand interactions between profile shape and SEM metrology. Experiments comparing top-down and cross-section SEM results showed an offset driven by the ability of the secondary electrons to escape the bottom of the trench (Figure 3A), and their simulation successfully captured the offset seen experimentally.
Smith emphasized that computational lithography has been an indispensable tool for understanding lithography and process development, and noted that multi-patterning (MP) will drive it further into manufacturing. He explained that non-lithography errors are becoming critical for MP schemes and reminded the audience of the link between overlay and CD (Figure 3B). He noted that computational patterning can support manufacturing in a variety of ways. In closing, he provided examples of how computational patterning will continue to move further into manufacturing, with solutions such as the Metrology Target Designer, wherein simulation allows virtual evaluation of many overlay and alignment targets, and mechanical models that relate film stress to overlay for feed-forward applications.
Dr. Ralph Dammel, Head of Technology Office USA at EMD Performance Materials, then provided an informative materials perspective of cost-effective lithography. Dammel reported that from the technology side, the complexity of further shrinking feature sizes can be handled, albeit at a rising cost. He warned that the economic implications of the rising cost per function may have a significant impact on industry dynamics. Dammel also explained that accelerating device technology requires ever-faster introduction of new materials. These new materials can ideally play the dual role of technology enablers providing new functionality, as well as economic enablers that reduce cost or complexity. Dammel then described ways in which materials innovation can enable performance at lower cost.
He detailed the change in materials through history and cited that spin-on dielectric (SOD) materials innovation had been key to staying on the industry roadmap. It was shown that a CMOS “periodic table” from the 1970s used only 17.5% of the non-radioactive elements. This grew to 22.5% in the 1980s, and 61% in the 2000s (Figure 4A). Dammel also noted that chemical vapor deposition (CVD) and atomic layer deposition (ALD) precursors are very diverse and they are one of the fastest growing IC materials markets. Looking into the future, Dammel predicts that there is definite potential for 2D materials such as graphene, silicene, germanene, and others, but a great deal of work is still needed. Carbon nano-tube transistors are also being developed by various groups as possible CMOS successors, and this could be possible by 2020.
Transitioning to less exotic approaches, Dammel explained the increased thickness of conventional Si-based hard masks leads to problems with pattern profiles, alignment mark detection, and metrology. Metal hard masks (MHM) alleviate these issues by enabling new etch options that can reduce process complexity (Figure 4B). Shrink materials, which modify resist structures after development to achieve feature sizes not accessible by direct lithography, were also identified as a cost-effective way around optical resolution limits. In addition, rinse materials perform the dual functions of preventing pattern collapse by reduction of the capillary (LaPlace) pressure and decreasing linewidth roughness (LWR) with line smoothing, making them indispensable in advanced processing particularly for EUV. Dammel further reported that EUV lithography requires new types of assist materials, including topcoats to absorb out-of-band radiation produced in the EUV source and to mitigate problematic resist outgassing and mirror contamination (Figure 5A). Dammel also reminded the audience of capabilities of DSA for “bottom up” patterning with information built into chemistry. He predicted contact-hole multiplication will be the first use of DSA and reported that high-χ block co-polymer development is on track to extend DSA capabilities.
In summary, Dammel stressed that materials development has played a key role in maintaining the roadmap, and said this will continue with new device structures and process flows requiring novel materials. Inventive use of new materials can help mitigate exploding costs below 20 nm, and he concluded that materials innovation is more important than ever.
Dr. Stephen Renwick of Nikon Research delivered the final presentation in this session, providing insight on scanner readiness for the next node. When considering 14 nm to 10 and on to the 7 nm nodes, Renwick questioned what scanner attributes are really important and whether enough has been done to meet the requirements. He described an SADP/cut scenario for a metal layer, looking at the effects of scanner errors on the final edge-placement error (EPE). Printing the mandrel with SADP was relatively easy — there was plenty of depth of focus and process window. When considering scanner error impacts on the CDU of the mandrel, he noted that only the CD of the spaces is affected (Figure 5B) and since scanner CDU 3σ performance is on the order of 0.9 nm, this supports the basic pattern.
He cautioned though, that the cuts are difficult to print and require serious OPC and SMO. Even at optimum conditions there is some edge placement error (EPE) due to OPC error. Renwick then investigated scanner-induced errors. He showed the effects of focus error on the cut exposure and commented that focus stability was below 5 nm max-min across two weeks, verifying that scanner focus performance is not an issue (Figure 6A). He reported that dose control is typically fractions of 1% across wafer and over time, scanner CD control can be less than 1 nm, so that dose and focus control are minimal error contributors. Overlay is frequently cited as a limiting factor. Renwick’s analysis showed that while overlay is important, it is not always the largest contributor to EPE. It tends to be about the same size as errors in the OPC. With mix-and-match overlay below 2.5 nm, the scanner meets requirements. Renwick compared how the error contributors stacked up and determined that OPC plays a very large part, and while overlay is a significant factor, it doesn’t necessarily ruin the printing (Figure 6B).
As mentioned by previous speakers, Renwick stated that partnership is imperative to achieve the necessary lithography goals. He described the Nikon Litho Turnkey Solution, which is built around the Plug and Play Manager. This open platform system engages track, metrology, and OPC partners to increase process windows, address hot spots, and enhance on-product control. Renwick summarized that for 10 nm and 7 nm printing, all of the methods including: multiple patterning, strong SMO and OPC, and continual scanner improvements are crucial. When ranking the top error contributors, it was evident that SMO/OPC and scanner overlay are roughly equivalent, followed by CDU uniformity. He reminded the audience that 193i scanners have already achieved some requirements and are well on the way towards others. He closed with the statement “193i litho remains viable for 10 nm and 7 nm nodes.”