Speaking at the Nikon technical symposium in February, Janice Golda, Intel Corporation Director of Lithography Strategic Sourcing, detailed semiconductor industry drivers. Golda reported that our appetite for technology, which enables actual product improvements, is expanding. True cost reduction remains possible, and she noted that lithography continues to be essential in delivering Moore’s Law. Golda explained that the move to the Digital Service Economy involves billions of connected devices, and new services to go with them (Figure 1A). As in Jevons Paradox, this increases technology efficiency, and rates of consumption leading to new usages. This yields four data center (DC) growth drivers, including the Cloud, NFV/SDN (Network Functions Visualization/Software Defined Networking), HPC (High Performance Computing), and Big Data, which substantially boost DC computational capacity purchases.
Graphics capabilities of end devices have substantial influence on semiconductor technology requirements. The device user’s experience is critical; eliminating wires, passwords, and creating a natural user interface are all enabled by more transistors. Golda highlighted that the internet of things (IoT) means that semiconductors are essentially everywhere–across home/industrial, mobile, gateway, network, and DC/Cloud applications (Figure 1B). It was noted that the second generation Intel tri-gate technology used in 14 nm transistors provides higher transistor performance (switching speed) and lower transistor leakage to support very diverse product requirements.
Golda emphasized that end user products drive performance, power, and form factor, as well was time to market, affordability, and the need to build a quintillion identical things. She reported the innovation-enabled technology pipeline is full (Figure 2A), and predicts that the future holds new equipment and materials, higher density and integration, as well as lower cost per transistor. However, this will not be easy going for lithographers. When considering capital growth ($/mm2), key factors consist of tool productivity and price, yield, defectivity, and the number of process steps; whereas transistor growth (mm2/transistor) drivers include resolution, multipatterning, and edge placement error. Together, litho scaling and cost of ownership will enable continuation of Moore’s Law (Figure 2B).
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Figure 2A. Golda reported the innovation-enabled technology pipeline is full (left image). Figure 2B. Litho scaling and cost of ownership will enable continuation of Moore’s Law. |
In closing, Golda stressed that lithography is the heart of Moore’s Law, and the industry must continue silicon technology leadership through investment and innovation, and achieve scaling density at about a factor of two per generation. She commented that scaling is imperative for improved performance, energy efficiency and reduced cost, and that it is vital to position processes to enable a wide spectrum of products. She concluded that keeping lithography affordable will enable true cost reduction.
In a complementary LithoVision presentation, Ryoichi Kawaguchi of Nikon Corporation shared his view of the lithography drivers and requirements along with the Nikon roadmap. Kawaguchi agreed that lithography scaling will continue beyond 10 nm, with mobile and IoT devices driving demand. He showed that even with optimistic assumptions for EUV throughput, DUV scanners will continue to dominate the lithography equipment market for several years (Figure 3A). He explained immersion lithography will be further extended with techniques like SAQP, cutting, and complementary methods such as DSA. The Nikon Litho Turnkey Solution will also be essential in optimizing on-product overlay (OPO), CD uniformity (CDU), and focus performance (Figure 3B).
Kawaguchi explained that as we transition from the 10 to the 7 nm node and beyond, OPO, focus, and CDU will become increasingly challenging. The scanner must provide pixelated illumination, compatability with strong optical proximity correction (OPC), and single-digit CD uniformity and overlay. In addition, scanner setup time needs to be reduced, while reliability, productivity, and upgradability must be optimized. He showed excellent across-lot NSR-S630D immersion single machine overlay (SMO) data below 1.7 nm (average + 3σ) for five tools, as well as mix-and-match overlay performance below 2.3 nm. Immersion productivity also continues to improve and S62X tools (throughput = 200 wafers per hour) are processing more than 4500 wafers per day.
Kawaguchi detailed the Nikon Litho Turnkey Solution, which is built around the Plug and Play Manager (Figure 4A). This open platform system engages track, metrology, and OPC partners to increase process windows, address hot spots, and enhance product control and manufacturing. He mentioned that XY and AF zeroing functions are also provided by Nikon to further improve overlay and focus performance under extreme exposure conditions. (Read More)
Kawaguchi reiterated that cost continues to be a significant factor for lithography. Single exposure EUVL (NA >0.3) will need to process more than 1500 wafers per day (WPD) to cost less than LELE 193i193i litho, and this will likely not occur in time for 10 nm insertion. At the 7 nm node EUVL would require an NA >0.5 and in addition multiple patterning, this will be cost prohibitive (Figure 4B). An alternative for EUVL may be single exposure at only half-field size with > 1200 WPD to compete with 193i LE×3 or LE×4.
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Figure 5. Kawaguchi concluded that immersion extension will continue with complementary litho techniques such as directed self-assembly. |
Kawaguchi emphasized that key scanner requirements for the next node are being met, and DUV system and technology solutions support continuous improvements and upgradability. In addition, the Nikon Litho Turnkey Solution optimizes on-product performance and reduces critical scanner setup time. Immersion technology is expected to maintain the lion’s share of the scanner equipment market, with 450 mm being an alternative option to reduce cost, and Nikon is prepared for the wafer size transition when the industry is ready. To close, he announced that immersion extension will continue (Figure 5) with complementary litho techniques such as directed self-assembly, as EUVL requires further performance and stability improvements.