Speaking at the Nikon technical symposium in February, Dr. Christopher Progler, CTO and VP of Strategic Planning for Photronics, Inc. delivered an up-to-date view of the State of Lithography that focused on lithography shrink strategies as they relate to mask technology. He observed that multi-patterning strategies tend to split into use of either very complex treatments with strong EDA use or simpler gridded layouts that need more layers. Both require strong co-optimization. EUV has different challenges including choices of the numerical aperture (NA) and reduction ratio to be used, but will still require strong interaction with computational lithography. He emphasized that whatever the strategy, every nanometer is important (Figure 1A).
No matter the details or the mask specs, Progler explained, the overriding concern is a high signal to noise (S/N) ratio of the transfer process from mask data to the wafer. This is because increasing mask complexity may yield diminishing returns and the information transfer capacity is eventually fixed. With that in mind, he estimated that a S/N ratio of about 10 is needed. Simply scaling basic mask specifications like CD uniformity, registration, and resolution isn’t sufficient to maximize information transfer, as for instance multi-patterning schemes have their own special requirements for mask registration.
CD control on the mask is of course vital to information transfer. A detailed breakdown of the CD control picture includes global and local signatures, fidelity (roughness/rounding), as well as linearity, pitch, and tone interactions, which are all obstacles in mask matching to ~1 nm (Figure 1B). In addition, litho choices drive mask CD control.
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| Figure 1A. Progler emphasized that whatever the strategy, every nanometer is important (left image). Figure 1B. A detailed breakdown of the CD control picture illustrates the obstacles in mask matching to ~1 nm. | |
Optimizing the effective bandwidth of the information transfer was his next topic. Looking at this, it was noted that 14 nm node logic variants can have more than 60 masking layers and apply 2x to 4x multi-patterning methods, with possibly 50% of the layers being critical or semi-critical. As the number of layers and the complexity increases, it becomes more difficult to sustain a robust tapeout environment. Progler commented on the importance of convergence to sub 2 nm maximum registration error on the mask, and described the benefits of a continuous registration modeling and feedback loop (Figure 2A). It is beneficial to unscramble systematic registration errors and isolate higher order correctable components. He conveyed that spectrum analysis has been used to diagnose dominant residual errors such as a phase error due to interaction between the mask writer and the resist (Figure 2B).
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| Figure 2A. Progler commented on the importance of convergence to sub 2 nm maximum registration on the mask, and described the benefits of a continuous registration modeling and feedback loop (left image). Figure 2B. Spectrum analysis has been used to diagnose dominant residual errors such as a phase error due to interaction between the mask writer and the resist. | |
Speed and cost are essential factors in manufacturing. The mask writing step is the most expensive one, with write times ranging from five to forty-five hours for a single mask. To address this, efforts are underway to develop new writing architecture using a high speed multibeam mask writing system. Progler announced that the program is entering the tool integration phase, with goals to deliver speed and capability. It was noted that pattern fidelity requirements are pushing masks towards low sensitivity resists, which will further amplify write time issues. Ultimately it’s all about the throughput and Progler stressed the criticality of innovating ways to hit the EUV/ArF mask cost breakeven threshold (Figure 3A).
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| Figure 3A. Progler stressed the criticality of innovating ways to hit the EUV/ArF mask cost breakeven threshold. | |
In closing, Progler advised the audience to “turn over every rock on signal to noise.” He recapped the importance of maximizing existing infrastructure for node shrinks, while also implementing new approaches to process mapping and control, and connecting the entire process from mask data to the wafer with continuous feedback. He also reiterated the need to reduce the barrier of entry for high mask count designs by optimizing the use of bandwidth through efficient designs, removing registration as a gating factor, and driving productivity for critical path steps.