At the recent LithoVision symposium, key technologists from several lithography companies highlighted tremendous capabilities, as well as the associated cost benefits, for immersion extension to 10 nm and beyond. Tokyo Electron Chief Engineer Hidetami Yaegashi opened the informative session, which focused on key immersion extension technologies. In his presentation entitled “Challenges and Solutions in Multi-Patterning Processes,” Yaegashi first discussed industry developments enabling miniaturization with “More Moore,” versus diversification with so-called “More than Moore” areas. He likened this to litho efforts involving “More Rayleigh” that focus on wavelength reduction, in contrast to diversification with “More than Rayleigh” solutions like sophisticated 193 nm patterning techniques, which were the subject of his presentation.
Although two dimensional (2D) logic IC layers have been successfully scaled down to the 20- and 14-nm nodes using litho-etch-litho-etch (LELE) pitch splitting, extension to sub-10 nm becomes problematic due to shrinking process windows. Unidirectional grating lines provide greater extendibility with multiple patterning, and Yaegashi described an effective scaling approach to sub-10 nm. He detailed a patterning process that consisted of immersion single exposure to the 38 nm half-pitch (hp), with self-aligned double patterning (SADP) down to the 19 nm hp, and self-aligned quadruple patterning (SAQP) to the 9.5 nm hp. He also revealed impressive self-aligned octuplet patterning results (SAOP) demonstrating 6.25 nm half-pitch patterning (Figure 1A), and emphasized that immersion extension to the 5 nm technology node is possible. In addition, Yaegashi highlighted scaling achievements in contact hole patterning: first using two exposure steps with SADP to achieve 16 nm hp; and then using single exposure with dual tone development and multiple deposition/etch steps to yield 20 nm hp contacts.
Yaegashi also detailed the edge placement control challenges associated with single directional layouts, and noted that pattern fidelity control in SADP is impacted by line edge roughness (LER), CD error, and placement error. He described how resist smoothing has been used as an intermediate process step for the SADP core pattern to reduce LER of the original lithography pattern from 1.9 nm to 1.4 nm, post etch. He also identified benefits to mask error factor, local CDU, and line placement roughness as a result of smoothing (Figure 1B). Yaegashi concluded by describing an effective hole shrink technique application for line cutting. He summarized his presentation by reminding the audience of the excellent capabilities of ArF multiple patterning at the sub-10 nm node.
This theme continued with a thought-provoking update on “Multiple Patterning: Extending the S-Curve,” from Chris Bencher, Applied Materials Distinguished Member of the Technical Staff. His presentation focused on the way interactive innovation extends product life cycle and adoption. Bencher used a series of examples showing how SADP continues to break through perceived capability “walls.” He informed the audience that SADP and ArF drove cost-effective NAND scaling for five technology nodes, with a 40% year-over-year reduction in Flash cost (Figure 2A). While many believed SADP was limited to NAND arrays, SADP has demonstrated DRAM active and MPU Fin patterning–validating immersion extension to 2x DRAM and Logic Fin patterning. Further, SADP has also exhibited MPU gate patterning capabilities that are likely to be implemented at 14/10 nm (Figure 2B). SADP was thought to be limited to 1D patterns, but use of complex (computer solved) mandrels have made it viable for back end of the line (BEOL) interconnect wiring down to the 50 nm pitch. Untapped ArF extension capabilities still exist here.
Similarly contact holes patterning was thought impossible for SADP, but Bencher showed an Active Contact SADP process used in Logic contact scaling producing 60 nm pitch contacts, 30 nm tip to tip (Figure 3A). Following that, the spacer process has been successfully extended to quadruple patterning (SAQP) with a low-cost transition and fast yield ramp . These ongoing spacer-process advancements clearly illustrate how interactive innovation extends a product life cycle.
Addressing further extension of ArF immersion for cut-masks and vias, Bencher confirmed ArF immersion can be extended for these layers using photoresist dry shrink, self-aligned vias (SAV), two-cut design libraries, and new litho materials like “invisible hardmasks.” Dry-shrink results for cut masks and self-aligned vias confirm there are no resolution barriers for ArF immersion down to 10 nm, and the invisible hardmask will further simplify and extend ArF immersion for SAV patterning. Continued design innovations that manage mask counts through layout optimization will also extend technology life cycles. In closing, Bencher reported that we are still in the very early stages of the ArF immersion S-Curve extension “saga” (Figure 3B).
Stephen Renwick, Senior Research Scientist at Nikon Research Corporation of America, wrapped up this session with analysis of “Complementary Options and Their Costs.” Renwick provided an overview of complementary lithography options for the 10 and 7 nm nodes (Figure 4A), and then reported his findings regarding feasibility and cost implications of various solutions. One candidate studied is the use of the 193i scanner in complementary lithography with directed self-assembly (DSA). The question to be answered was whether the complementary litho scheme would impose new requirements on the scanner. He had investigated DSA requirements for the scanner at the 10/7 nm nodes by constructing a model to characterize overlay error and 2nd print CD error using DSA combined with double patterning (DP). He found that overlay accuracy ≤ 2 nm and single digit CD uniformity were required, and reported that Nikon scanner performance is already achieving these levels (Figure 4B).
Beyond scanner capabilities, a persistent question for the industry is the cost of various complementary solutions, and the results reported by Renwick were very compelling. When considering the costs associated with the hardware required to meet 200 wafers per hour (WPH) throughput, 193i-single patterning requires one 200 WPH tool, whereas 193i double exposure requires two 200 WPH tools, and EUV single exposure will need five 40 WPH tools. The 10 nm node litho options shown in the table in the Figure 4A can be simplified as: 193iDP, 193i DP+, 193iDP++, 193iTP (triple patterning), and EUV SP (single patterning). When considering these 10 nm node options with 200 WPH 193i and 40 WPH EUV, even 193 nm triple patterning can be less costly than EUV (Figure 5A). Furthermore, 193DP++ has a better cost ratio than EUV until EUV delivers more than 100 WPH. Looking beyond to the 7 nm node, although choices become more complicated, here again 193i extension is a contender. Renwick concluded this session by reiterating that continuous improvements in 193i scanners has kept them ready for multiple processing, and that they will be used with complementary lithography solutions such as DSA. Furthermore, cost analysis has shown that 193i extension is competitive with and usually less expensive than EUV (Figure 5B).